Semiconductor power devices such as vertical DMOS, V-groove DMOS, and trench DMOS MOSFETs, IGBTs as well as diodes and bipolar transistors are employed in applications such as automobile electrical systems, power supplies, motor drives, and other power control applications. Such devices are required to sustain high voltage in the off-state while having low on-resistance or a low voltage drop with high current density in the on-state.
FIG. 1 illustrates a typical structure for an N-channel power MOSFET. An N-epitaxial silicon layer 101 formed over an N+ doped silicon substrate 102 contains p-body regions 105a and 106a, and N+ source regions 107 and 108 for two MOSFET cells in the device. P-body regions 105 and 106 may also include deep p-body regions 105b and 106b. A source-body electrode 112 extends across certain surface portions of epitaxial layer 101 to contact the source and body regions. The N-type drain for both cells is formed by the portion of N-type epitaxial layer 101 extending to the upper semiconductor surface in FIG. 1. A drain electrode is provided at the bottom of N+ doped substrate 102. An insulated gate electrode 118 comprising insulating and conducting layers, e.g., oxide and polysilicon layers, lies over the body where the channel will be formed and over drain portions of the epitaxial layer.
The on-resistance of the conventional MOSFET shown in FIG. 1 is determined largely by the drift zone resistance in epitaxial layer 101. Epitaxial layer 101 is also sometimes referred to as a voltage sustaining layer since the reverse voltage applied between the N+ doped substrate and the P+ doped deep body regions is sustained by epitaxial layer 101. The drift zone resistance is in turn determined by the doping concentration and the thickness of epitaxial layer 101. However, to increase the breakdown voltage of the device, the doping concentration of epitaxial layer 101 must be reduced while the layer thickness is increased. The curve in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage for a conventional MOSFET. Unfortunately, as the curve shows, the on-resistance of the device increases rapidly as its breakdown voltage increases. This rapid increase in resistance presents a problem when the MOSFET is to be operated at higher voltages, particularly at voltages greater than a few hundred volts.
FIG. 3 shows a MOSFET that is designed to operate at higher voltages with a reduced on-resistance. This MOSFET is disclosed in Cezac et al., Proceedings of the ISPSD, May 2000, pp. 69-72, and Chen et al., IEEE Transactions on Electron Devices, Vol. 47, No. 6, June 2000, pp. 1280-1285, which are hereby incorporated by reference in their entirety. This MOSFET is similar to the conventional MOSFET shown in FIG. 1 except that it includes a series of vertically separated P− doped layers 3101, 3102, 3103, . . . 310n (so-called “floating islands”), which are located in the drift region of the voltage sustaining layer 301. The floating islands 3101, 3102, 3103, . . . 310n produce an electric field that is lower than for a structure with no floating islands. The lower electric field allows a higher dopant concentration to be used in the epitaxial layer that in part, forms the voltage sustaining layer 301. The floating islands produce a saw-shaped electric field profile, the integral of which leads to a sustained voltage obtained with a higher dopant concentration than the concentration used in conventional devices. This higher dopant concentration, in turn, produces a device having an on-resistance that is lower than that of a device without one or more layers of floating islands.
The structure shown in FIG. 3 can be fabricated with a process sequence that includes multiple epitaxial deposition steps, each followed by the introduction of the appropriate dopant. Unfortunately, epitaxial deposition steps are expensive to perform and thus a structure that uses multiple epitaxial deposition steps is expensive to manufacture.
Accordingly, it would be desirable to provide a method of fabricating a power semiconductor device such as the MOSFET structure shown in FIG. 3, which method requires a minimum number of epitaxial deposition steps so that the device can be produced less expensively.